1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device having a ferroelectric memory and its testing method, and more particularly to a non-volatile semiconductor memory device having a structure capable of surely screening the deterioration due to use of a ferroelectric material without making a screening test of applying stress for a long time.
2. Description of the Related Art
FIG. 8 shows an example of a memory cell of a semiconductor memory such as a ferroelectric memory and a flash memory. Each of such memory cells arranged in the semiconductor memory is composed of a switching transistor Tr and a ferroelectric capacitor Ca. Write/read for the memory cell is carried out by a drive circuit including a sense amplifier SE. In such a semiconductor memory, if the write is made in a state with a lowered power supply voltage due to exhaustion of a battery, the operation becomes abnormal, thus leading to erroneous write (insufficient write). In order to prevent such an inconvenience, a control circuit is provided which includes a detection circuit for detecting a power supply voltage and stopping the operation of the memory cell when the power supply voltage becomes lower than a prescribed value. As seen from FIG. 9A, such a control circuit 50 detects the power supply voltage Vcc in such a manner that the voltage at a monitoring point P where the power supply voltage is resistance-divided is monitored, and stops to supply the power supply voltage to a memory cell 51 and a logic circuit 52 when it becomes lower than a prescribed voltage. In order to assure the reliability of the semiconductor memory, as shown in FIG. 9B, the prescribed voltage is set at a higher voltage B than an actually enable voltage A. The range AC between A and C (normal voltage) is actually used. In FIG. 9B, segments AC, OA and OB correspond to an enable region, disable region and lockout region where the power is not supplied to the memory cell 51 and logic circuit 52, respectively.
Such semiconductor memories are subjected to a screening test under a strict condition where thermal stress is applied for a long time, thereby screening faulty products. In the case of the flash memory, its faulty products are screened at the early stage of the test.
However, in the case of a device using a ferroelectric material, as shown in FIG. 10, faulty products are detected not only early (dotted line B) but during a time passage (dotted line B) so that faulty products are distributed as shown in curve C. As guessed from this test result, the ferroelectric film constituting a ferroelectric memory is very susceptible to heat, and so likely to be deteriorated by exposure to the high temperature. Therefore, in order to screen completely the faulty products, which may be generated after elapse of a long time, completely, the screening test must be made for a long time. The screening test may shorten the life of the good products. This hinders improvement of the reliability of the ferroelectric memory. On the other hand, the ferroelectric memory has a characteristic that its polarization decreases as the temperature rises, as seen from a graph of FIG. 11. In addition, the ferroelectric memory has also a characteristic that its residual polarization decreases greatly as an applied voltage lowers, as seen from graphs of FIGS. 12 and 13. Specifically, FIG. 12 shows a hysterisis curve of a relationship between an applied voltage and a residual polarization in the ferroelectric memory having a ferroelectric thin film formed by RTA (Rapid Temperature Anneal). FIG. 13 shows a hysterisis curve of a relationship between an applied voltage and a residual polarization in the ferroelectric memory having a ferroelectric thin film formed by heating within a furnace. FIGS. 14 and 15 show a saturation characteristic of a polarization and an applied voltage in a ferroelectric memory having a ferroelectric thin film formed by RTA and furnace processing, respectively. In FIG. 14, the abscissa designates an applied voltage while the ordinate designates residual polarization. In FIG. 15, the abscissa designates an applied voltage while the ordinate designates a saturation voltage. In FIGS. 14 and 15, black marks indicate the RTA processing while white marks indicate furnace processing.
As seen these graphs, when the applied voltage is lowered, the residual polarization decreases greatly as the applied voltage is lowered so that an operation condition is made severe. This permits the presence of faulty products to be remarkable. Specifically, as seen from FIG. 10, the test at a normal high voltage (e.g. 5 V) permits the screening of faulty products in the state of "D". On the other hand, the test at a low voltage (e.g. 3 V), which makes the saturation polarization half as seen from FIG. 14, permits the screening of faulty products in the state of "E". This has an effect of gaining the screening time. The present invention has been accomplished on the basis of such a discovery.
However, such a kind of semiconductor memory is provided with a detection circuit so that it can otherwise operate, but does not operate at a voltage lower than the actually used region relying on the safety of the operation, as described above. In the detection circuit, the voltage is fixed at a prescribed value. Therefore, the detection circuit cannot be operated at a lower voltage than the above actually used region. Thus, in the screening test described above, the testing voltage can be only lowered to the lowest voltage in the actually used region. This makes the test insufficient. However, if the lower limit of the actually used region is lowered, danger of erroneous write for the semiconductor memory occurs so that sufficient reliability for the memory cannot be obtained.
The present invention has been accomplished in order to solve such a problem.
An object of the present invention is to provide a non-volatile semiconductor memory which can be sufficiently tested without being damaged by a screening test for a long time, and has high reliability or low mortality rate for data holding.
In order to attain the above object, in accordance with the present invention, there is provided a non-volatile semiconductor memory device comprising: a ferroelectric memory cell and a cut-off circuit for cutting off the power supply voltage when the detected power supply voltage is lower than a prescribed write inhibit voltage, further comprising a control means capable of stopping a cut-off operation of said cut-off circuit in response to a control input signal when the detected power supply voltage is lower than the write inhibit voltage.
A first aspect of device is a non-volatile semiconductor memory device of the present invention, which comprises: a ferroelectric memory cell; a detection circuit for detecting a power supply voltage as a monitored voltage; a cut-off circuit for cutting off the power supply voltage when the detected power supply voltage is lower than a prescribed write inhibit voltage, thereby preventing the memory cell from being operated, and a control means capable of stopping a cut-off operation of said cut-off circuit in response to a control input signal when the detected power supply voltage is lower than the write inhibit voltage, said control means being arranged between the cut-off circuit and the memory cell.
In accordance with the present invention, the non-volatile semiconductor memory holds a lock-out function in a normal operating state. Namely, when the power supply voltage becomes lower than a prescribed voltage, the operation of the memory is stopped. At the same time, the screening test can be carried out at a lower operating voltage than in the normal operation. Because the characteristic of a ferroelectric material is attenuated owing to the drop of the operating voltage, the screening test for a short time can sufficiently screen the products which may be faulty. As a result, since the product is not deteriorated by the screening test, the life of the product can be lengthened and surely selected, thereby improving the reliability of the product. Shortening the time for the screening test greatly contributes to reduction of the production cost.
A second aspect of the device is a non-volatile memory device according to the first aspect, wherein said control means includes a means for invalidating said cut-off circuit in response to said control input signal irrespectively of said power supply voltage so that said power supply voltage is not cut off.
A third aspect of the device is a non-volatile memory device according to the first aspect, wherein said control means includes a means for boosting said monitored voltage in response to said control input signal when said power supply voltage is lowered so that said monitored voltage is higher than said write inhibit voltage.
A fourth aspect of the device is a non-volatile memory device according to the first aspect, wherein said control means includes a voltage boosting means for boosting said monitored voltage stepwise in response to said control input signal.
A fifth aspect of the device is a non-volatile memory device according to the first aspect, wherein said detection circuit includes divided resistors connected between a terminal of said power supply voltage and a grounding terminal to detect said monitored voltage as a divided voltage, and said voltage boosting means adjusts a division ratio of said divided resistors.
A sixth aspect of the method is a method of testing a non-volatile semiconductor memory device including a ferroelectric memory cell; a detection circuit for detecting a power supply voltage as a monitored voltage; and a cut-off circuit for cutting off the power supply voltage when the detected power supply voltage is lower than a prescribed write inhibit voltage, thereby preventing the memory cell from being operated, comprising the steps: deactivating a cut-off operation of said cut-off circuit when said power supply voltage becomes a first voltage lower than said write inhibit voltage; applying a low voltage to said memory cell in such a manner that said first voltage is applied to said memory cell for a prescribed time; and testing an operation characteristic of said memory cell subjected to said low voltage applying step to check whether it is normal or not.
A seventh aspect of the method is a method of testing a non-volatile semiconductor memory device according to the sixth aspect, wherein said deactivating step includes invalidating said cut-off circuit in response to said control input signal irrespectively of said power supply voltage so that said power supply voltage is not cut off.
An eighth aspect of the method is a method of testing a non-volatile semiconductor memory device according to the sixth aspect, wherein said deactivating step includes adjusting said monitored voltage in response to said control input signal when said power supply voltage is lowered so that said monitored voltage is higher than said write inhibit voltage.
An ninth aspect of the method is a method of testing a non-volatile semiconductor memory device according to the sixth aspect, wherein said deactivating step includes boosting said monitored voltage by a necessary magnitude in response to said control input signal.
An tenth aspect of the method is a method of testing a non-volatile semiconductor memory device according to the ninth aspect, wherein said deactivating step includes adjusting said monitored voltagein such a manner that a division ratio of divided resistors connected between a terminal of said power supply voltage and a grounding terminal is adjusted in response to said control input signal.